Fault-tolerant computer architecture

Details Fault-tolerant computer architecture Fault-tolerant computer architecture

1996-01-18

1997-05-13

Beausoliel, Jr., Robert W.

Excavating

371 36, 371 681, G01R 3128, G06F 1100

Patent

active

056300468

ABSTRACT:
In order to perform a predetermined function, to detect failures, and to further perform the function after detection of a failure, a computer comprises two redundant processing chains and a monitoring device monitoring operating of the two chains, each chain comprising an acquisition circuit, a transmission circuit, and a processor performing the function and monitoring operating of the acquisition and transmission circuits of the other chain, and of the monitoring device, and issuing operating statuses of the elements monitored, the computer further comprising a voting device receiving the operating statuses in order to determine which elements have actually broken down, and a selection device intended to only output from the computer the results provided by a chain operating properly.

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Victor Maggioli, The Safety Matrix--A method for Guidelining Industrial Microcomputers IEEE Transactions on Industry Applications, vol. 25 No. 3, pp. 514-522, May/Jun. 1989.
Frederickson et al, Comparison of Fault Tolerant Controllers Used in Safety Applications, ISA Transactions, vol. 30 No. 4, pp. 97-106, 1991.

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