Fault tolerant computer architecture

Details Fault tolerant computer architecture Fault tolerant computer architecture

1987-09-04

1989-07-18

Smith, Jerry

Excavating

371 9, G06F 1116

Patent

active

048499790

ABSTRACT:
A fault tolerant computer architecture in which a functional unit is duplicated and the input and output signals to and from the two units are compared with each other by comparators to provide an error signal in case of different behavior of the two units, resulting in different input/output signals. The operation of both functional units is controlled by a first read only control memory or alternatively by a second read/write control memory once it has been loaded with microprograms, under control of the first read only control memory. The correct behavior of the comparators is tested in a diagnostic mode by having one functional unit operated under control of the first memory and the other functional unit operated under control of the second memory, so that the two units are controlled to perform different functions which force the comparators to produce an error indication, the absence of which indicates that the comparators operation is faulty.

REFERENCES:
patent: 4096989 (1978-06-01), Tawfik
patent: 4099234 (1978-07-01), Woods et al.
patent: 4222515 (1980-09-01), Strelow
patent: 4233682 (1980-11-01), Liebergot
patent: 4400792 (1983-08-01), Strelow
patent: 4541094 (1985-09-01), Stiffler

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