Fault-tolerant clock system

Details Fault-tolerant clock system Fault-tolerant clock system

1978-06-14

1980-12-16

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 328 61, 328 62, 328104, H03K 300

Patent

active

042399823

ABSTRACT:
A fault-tolerant clock system for providng digital timing signals (system clock signals) is provided by a plurality of clock sources. Each clock source receives as inputs the generated clock signals from all the other clock sources and contains receiver circuitry to derive a system clock signal from said clock sources which is the consensus clock signals of the other sources. Each clock source generates and distributes to the other clock sources a clock signal which is phase locked to the derived system clock from its clock receiver. In a system of (2r+2) clock sources (r+2) of them will remain phase locked to each other despite up to r clock source failures. Any clock receiver responsive to any (2r+1) of the clock sources can therefore derive a correct system clock despite up to r clock source failures.

REFERENCES:
patent: 3278852 (1966-10-01), Mann
patent: 3479603 (1969-11-01), Overstreet, Jr.
patent: 3803568 (1974-04-01), Higashide
patent: 3900741 (1975-08-01), Fletcher et al.
patent: 3961270 (1976-06-01), Ullmann et al.
patent: 4019143 (1977-04-01), Fallon et al.

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