Fault-tolerant clock signal distribution arrangement

Details Fault-tolerant clock signal distribution arrangement Fault-tolerant clock signal distribution arrangement

1978-05-15

1980-01-22

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307219, 307269, 328104, H03K 500

Patent

active

041852451

ABSTRACT:
A fault-tolerant clock signal distribution system for a plurality of equipment units is disclosed. Fault tolerance is achieved by independent bussing of clock signals from each of a pair of duplicated clock sources to a plurality of clock receiver units, each receiver unit associated with one of the plurality of equipment units and including sequential logic apparatus operative to examine the two clock signal trains bussed to the clock receiver unit and to ignore that signal train that phase lags the other. In case the phase leading clock source or its transmission bus fails, the remaining clock signal takes over. Because the outputs of the duplicated clock sources are distributed over separate busses, either source may comprise the phase-leading clock at any particular clock receiver unit. The phase difference between the two clock source outputs is kept small enough such that any resultant irregularity in the clock receiver unit output upon failure of one of the two clock sources or transmission busses will not affect the normal operation of the equipment units served by the clock distribution arrangement.

REFERENCES:
patent: 3479603 (1969-11-01), Overstreet, Jr.
patent: 3803568 (1974-04-01), Higashide
patent: 3900741 (1975-08-01), Fletcher et al.
patent: 3965432 (1976-06-01), Denenberg et al.
patent: 4019143 (1977-04-01), Fallon et al.
patent: 4025874 (1977-05-01), Abbey

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