Fault tolerant clock distribution system

Details Fault tolerant clock distribution system Fault tolerant clock distribution system

1993-12-23

1995-06-06

Chin, Stephen

Pulse or digital communications

Synchronizers

Synchronization failure prevention

375356, 331 49, 307 65, 327292, 327295, 327258, H04L 700

Patent

active

054229154

ABSTRACT:
A fault tolerant multiple phase clock distribution system for providing synchronized clock signals to multiple circuit loads. Multiple electrically isolated power domains are powered by redundant AC and DC power sourcing circuits to ensure continued operation upon partial failure of the AC or DC power sourcing circuits. Multiple oscillators from the multiple power domains are synchronized to produce a group of simultaneously synchronized clock signals. Multiple synchronized clock signals from this group are then selected by selection circuitry and selection control circuitry, and are distributed to multiple circuit loads requiring simultaneous synchronization. The oscillator circuitry, synchronization circuitry, selection circuitry, and distribution circuitry is all provided in redundant form, so that the partial failure of any of the circuitry will not result in a system stop. Error recovery circuitry monitors for proper synchronization of the synchronized clock signals, and provides for automatic or manual error recovery upon detection of a synchronization error. A single phase synchronized clock signal is generated to minimize synchronization complexities, and circuitry exists at the circuit loads to generate multiple phase enable signals to emulate a multiple phase clock.

REFERENCES:
patent: 4254492 (1981-04-01), McDermott, III
patent: 4412342 (1983-10-01), Khan et al.
patent: 4644498 (1987-02-01), Bedard et al.
patent: 4707142 (1987-11-01), Baker et al.
patent: 4754164 (1988-06-01), Flora et al.
patent: 4882738 (1989-11-01), Suzuki
patent: 5036528 (1991-07-01), Constantino

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