Fault-tolerant cell addressable array

Details Fault-tolerant cell addressable array Fault-tolerant cell addressable array

1975-07-03

1977-09-06

Fears, Terrell W.

Communications: electrical

Digital comparator systems

340173BB, 364900, G11C 1140, G11C 1300

Patent

active

040471632

ABSTRACT:
A small programmable memory means such as an electrically programmable logic array is incorporated on the chip of a conventional bit addressable random access memory or other cell addressable array circuit. The array has one or more superfluous rows and/or columns of cells held in reserve. Processing and testing of the chip is conducted in a conventional manner. Chips with faulty cells are corrected by programming the memory means with the cell addresses of the faulty cell locations. Subsequently, the memory means will respond to any of these addresses and, through interaction with input/output logic, cause the data input and/or output to be steered to or from a reserve cell instead of the addressed faulty cell.

REFERENCES:
patent: 3436734 (1969-04-01), Pomerewe
patent: 3659275 (1972-04-01), Marshall
patent: 3748653 (1973-07-01), Debruyne
patent: 3781826 (1973-12-01), Beausoleil
patent: 3800294 (1974-03-01), Lawlor
patent: 3813650 (1974-05-01), Hunter
patent: 3845476 (1974-10-01), Boehm
patent: 3882470 (1975-05-01), Hunter
patent: 3897626 (1975-08-01), Beausoleil

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