Fault-tolerant cell addressable array

Details Fault-tolerant cell addressable array Fault-tolerant cell addressable array

1975-07-03

1977-09-27

Atkinson, Charles E.

Registers

Systems controlled by data bearing records

Time analysis

364900, 340173BB, G11C 2900, G11C 800, G06F 1100

Patent

active

040513548

ABSTRACT:
A small programmable memory means such as an electrically programmable logic array is incorporated on the chip of a conventional bit addressable random access memory or other cell addressable array circuit. The array has one or more superfluous rows and/or columns of cells held in reserve. Processing and testing of the chip is conducted in a conventional manner. Chips with faulty cells are corrected by programming the memory means with the cell addresses of the faulty cell locations. Subsequently, the memory means will respond to any of these addresses and, through interaction with either the address decoding logic or input/output logic, cause a reserve cell or the contents thereof to be selected instead of the faulty cell.

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patent: 3845476 (1974-10-01), Boehm
patent: 3860831 (1975-01-01), Goser
patent: 3868646 (1975-02-01), Bergman
patent: 3872291 (1975-03-01), Hunter
Sherman, Scheme for "Blowing" Fusible-Links, IBM Technical Disclosure Bulletin, vol. 14, No. 10, Mar. 1972, pp. 3200-3201.

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