Fault tolerant address translation method and system

Details Fault tolerant address translation method and system Fault tolerant address translation method and system

1993-06-14

1995-10-03

Trammell, James P.

Excavating

39518203, H03M 1300

Patent

active

054558344

ABSTRACT:
A method and system are disclosed wherein error detection codes are used for detecting and handling hardware errors in a memory table. Before each address and associated data are entered into the memory table, an error detection code is generated for both the address and the data. The address, data, and corresponding error codes are stored in the same entry line in the memory table. When the table receives an input address from a CPU, the input address is compared to all of the addresses stored within the memory table. If any stored address matches the input address, the matched address is outputted along with its associated data and its corresponding error codes. The matched address and its associated data are each processed with its corresponding error code to determine whether the outputted address and data are identical to the address and data used to generate the error codes. If either the address or the data has been altered by a hardware error in the memory, an error signal is generated to indicate that the outputted information is invalid. This error signal causes the outputted information to be ignored. The hardware error is thus detected and tolerated. The memory table also includes a fault tolerant coherence table which contains physical addresses and corresponding error codes. Each address and corresponding error code in the coherence table is periodically outputted and processed by an error processor to check for possible errors. If an address in the coherence table contains an error, the address is invalidated. By periodically monitoring the coherence table, errors are detected and reliability is improved.

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