Fault testing a clock distribution network

Details Fault testing a clock distribution network Fault testing a clock distribution network

1983-10-31

1985-09-17

Atkinson, Charles E.

Excavating

371 15, G01R 3128

Patent

active

045425094

ABSTRACT:
A method and apparatus for fault testing a clock distribution network which provides a plurality of clock signal lines to the logic networks which comprise a data processor. The fault testing apparatus includes a decoder for selecting one of the clock signal lines to be tested, and a test latch which is clocked by the selected clock signal line. The selected clock signal line is tested by setting the test latch to a first logic value (e.g., binary ZERO) and maintaining a second logic value (e.g., binary ONE) at the test latch input. If the second logic value is stored in the test latch when the clock distribution network is inhibited, then a stuck-on fault is indicated for the selected clock signal line. If the second logic value fails to be stored in the test latch when the clock distribution network is enabled, then a stuck-off fault is indicated for the selected clock signal line. Each clock signal line in the clock distribution network may be tested in this manner.

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Dimitri, Delay Testing and Diagnosis of LSSD Shift Register Strings, IBM Technical Disclosure Bulletin, vol. 20, No. 1, Jun. 1977, pp. 307-312.
Herceg et al., Complete Fault Detection and Fault Location for System Oscillator, IBM Technical Disclosure Bulletin, vol. 22, No. 1, Jun. 1979, pp. 80-82.
Kam, Clock Running Detector, IBM Technical Disclosure Bulletin, vol. 22, No. 11, Apr. 1980, pp. 4866-4868.

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