Fault simulator for digital circuitry

Details Fault simulator for digital circuitry Fault simulator for digital circuitry

1997-04-15

1999-04-20

Beausoliel, Jr., Robert W.

Excavating

395500, G06F 1100

Patent

active

058964010

ABSTRACT:
A fault simulator for a digital combinational circuit implements a critical path tracing algorithm in reconfigurable hardware and comprises: a forward network capable of emulating the digital combinational circuit and having primary outputs; a second forward network capable of emulating the digital combinational circuit in the presence of a stem fault and having corresponding primary outputs, the first and second forward network receiving identical input test signals at primary inputs thereof; a backward network having one primary input for every primary output of said combinational circuit and one primary output for every primary input of the combinational circuit, the backward network receiving signal values propagated to primary outputs in the first forward network in response to the input test signals; and, circuitry provided in the backward network responsive to signal values propagated in the first forward network for computing criticality of paths, the computed critical paths indicating faults in the combinational circuit that are detected by the input test signals.

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Fadi Maamari et al., Areconvergent fanout analysis for efficient exact fault simulation of combinational circuits, IEEE, 18 Fault tolerant computing symp. 122-127, Jun. 1988.
D. Dumas et al., An implicit delay fault simulation method with approximate detection threshold calculation, IEEE, International test conference, Jun. 1993.
Udo Mahlstedt et al., Simulation of non-classical faults on the gate level-the fault simulator COMSIM, IEEE trans. International test conference, Jun. 1993.
L. Burgun, F. Reblewski, G. Fenelon, J. Barbier and O. Lepape, "Serial Fault Simulation," Proc. Design Automation Conf., pp. 801-806, 1996.

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