Fault simulation method

Details Fault simulation method Fault simulation method

1990-10-01

1993-02-02

Teska, Kevin J.

Boots, shoes, and leggings

364578, 371 23, G06F 1560

Patent

active

051843080

ABSTRACT:
A logic circuit to be an object for fault simulation is logically modified into a logic circuit configuration using logic gates of a predetermined basic gate form. Pin management data indicative of a correspondence of pins of the logic gates to a position of fault assumption of each of the pins prior to logic modification is formed. Logic simulation is then performed by injecting a fault logic value into the position of fault assumption of each of the pins of the gate of the logic circuit subsequent to the logic modification corresponding to each of the pins prior to the logic modification with reference to the pin management data, thereby implementing a fault simulation for detecting the fault of the logic circuit.

REFERENCES:
patent: 4791578 (1988-12-01), Fazio et al.
patent: 4815016 (1989-03-01), Young
patent: 4937765 (1990-06-01), Shupe et al.
patent: 4942536 (1990-07-01), Watanabe et al.
patent: 4954953 (1990-09-01), Bush
patent: 4996659 (1991-02-01), Yamaguchi et al.
patent: 5018089 (1991-05-01), Kanazawa
"Logic Simulation Speeded With New Special Hardware", J. R. Lineback; Electronics vol. 55, No. 12 (Jun. 16, 1982). pp. 45-46.

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