Fault recovery mechanism, transparent to digital system function

Details Fault recovery mechanism, transparent to digital system function Fault recovery mechanism, transparent to digital system function

1988-10-11

1991-02-26

Smith, Jerry

Excavating

364200, 3642665, 3642685, 364900, 364945, 3649453, 371 13, G06F 1114, G06F 1116

Patent

active

049966871

ABSTRACT:
A method and apparatus allows fault recovery in a digital computer based control system whereby system upsets induced by external transient noise conditions can be accommodated. A CPU is coupled to its main memory and its I/O interfaces by a common address/data bus, these three elements being susceptible to having data thereon or therein corrupted by transient noise. Also coupled to the bus, but in a hardened environment, are first and second supplemental memories which, under memory control, operate on alternating even and odd computational frames defined by the CPU's real-time clock to store the same words as are then being entered into the CPU's main memory. As computational frames are entered into one or the other of these two memories by eaves-dropping on the common bus, the other supplemental memory is transferring its contents to a backup memory which is also housed in the noise-immune environment. The backup memory is connected in a read-only mode to the address/data bus and, because of the manner of operation, always contains the computational frame that is delayed one cycle of the CPU's real-time clock from the frame in progress. Should a transient upset occur, it may be followed by a transfer of the information from the backup memory into the computer's main memory such that computations can then continue with data that is uncorrupted.

REFERENCES:
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patent: 4199810 (1980-04-01), Gunckel, II et al.
patent: 4413327 (1983-11-01), Sabo et al.
patent: 4442501 (1984-04-01), Eckert, Jr. et al.
Bernstein, P., "Seguoia: A Fault-Tolerant Tightly Coupled Multiprocessor for Transaction Processing", Computer, Feb. 1988, pp. 37-45.

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