Fault recovery in systems utilizing redundant processor arrangem

Details Fault recovery in systems utilizing redundant processor arrangem Fault recovery in systems utilizing redundant processor arrangem

1990-05-02

1992-10-13

Dixon, Joseph L.

Excavating

371 163, G06F 1100

Patent

active

051557290

ABSTRACT:
Apparatus to prevent endless switchover attempts between processors in redundant processor systems where each processor resets an associated watch dog timer (WDT). Whenever a WDT times out, WDT sends a restart signal to its associated processor and a failure signal to switchover control logic. The switchover control logic causes a switch from the active processor to the standby processor if the standby processor is healthy and is properly resetting its WDT and, if the standby processor is not, the switchover control logic will generate a signal to cause a cold reboot of the entire system. However, if the standby processor is healthy, the switchover control logic will generate a signal to cause a switchover to the standby and will generate a signal to increment a switchover counter. The value of the switchover counter is compared with a predetermined threshold value. If the value of the switchover counter matches the predetermined threshold value, a signal is generated to cause a cold reboot of the entire system. A timer associated with the switchover counter periodically clears the switchover counter. Thus, if the system is switching back and forth between the redundant processors at a rate which causes the switchover counter to exceed the predetermined threshold before the switchover counter can be cleared by the timer, the system will perform a cold reboot.

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