Fault management scheme for a cache memory

Details Fault management scheme for a cache memory Fault management scheme for a cache memory

1996-07-08

1997-05-13

Nguyen, Hoa T.

Excavating

395458, 395471, 36424544, 3642653, 364DIG1, 371 402, G06F 1110

Patent

active

056299508

ABSTRACT:
The present invention is directed to a method of managing a cache upon detection of an address TAG parity error, The cache includes a plurality of entries for storage of data, with each entry having a corresponding address TAG entry. The method includes the steps of performing a TAG parity check for each access to the cache, and upon detection of a parity error in an address TAG, disabling allocation of TAG entries for storage of new address TAGs. A signal indicating the TAG parity error is transmitted to an error correction mechanism.

REFERENCES:
patent: 4357656 (1982-11-01), Saltz et al.
patent: 4543628 (1985-09-01), Pomfret
patent: 5155843 (1992-10-01), Stamm et al.
patent: 5175859 (1992-12-01), Miller et al.
patent: 5226150 (1993-07-01), Callander et al.
patent: 5253203 (1993-10-01), Partovi et al.
Implementation of Last Tag Indicators Using Illegal Tag Table Entries, Research Disclosure Oct. 1989.

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