Fault isolation using pseudo-random scan

Details Fault isolation using pseudo-random scan Fault isolation using pseudo-random scan

1997-01-22

1997-12-02

Nguyen, Hoa T.

Excavating

371 225, 39518306, G01R 3128

Patent

active

056944012

ABSTRACT:
A digital system, comprising a plurality of integrated circuits that are designed to be scannable for pseudo-random scan testing. Testing begins and proceeds in normal binary-tree fashion, subjecting the system to a pseudo-random scan test and developing from that test a signature that is compared to a standard signature. If the comparison is unequal, portions of the system are subjected to pseudo-random scan testing, in normal binary-tree fashion, until the integrated circuit level is reached whereat a final mis-compare for the signature developed for a integrated circuit is obtained. Then, each bit position of the scan for such integrated circuit is classified according to the source of data for its primary input, and pseudo-random scan testing conducted to extract signatures for each such classified source. When a bad signature is reached, after comparing to standard signatures, the fault has been isolated to the classified source.

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patent: 4817093 (1989-03-01), Jacobs et al.
patent: 4947357 (1990-08-01), Stewart et al.

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