Fault injection using boundary scan

Details Fault injection using boundary scan Fault injection using boundary scan

1993-10-12

1995-06-27

Voeltz, Emanual T.

Excavating

371 165, 371 3, 371 291, 371 27, 364578, 364579, 364580, 3241581, G01R 3128

Patent

active

054286247

ABSTRACT:
A system and method for fault injection utilizing boundary scan includes the provision of an additional fault injection register to the standard JTAG architecture in order to allow the intentional introduction of faults into a device or module forming part of a system under test. Through the use of the fault injection register of the present invention, faults may be intentionally introduced and the system response to such faults monitored and analyzed independently of the system software and without the use of mechanical probes or the like for introducing the fault. The system and method of the present invention is readily integrated with the existing test functions of the standard IEEE 1149.1 boundary scan architecture.

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Hewlett-Packard Company, HP Boundary-Scan Tutorial and BSDL Reference Guide, HP 307x Board Test System, Dec. 1990, Ch. 1-3, Appendix.
Mauder, Colin M. and Tulloss, Rod E., Testability on Tap, IEEE Spectrum, Feb., 1992, pp. 34-37.

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