Multiplex communications – Wide area network – Packet switching
Patent
1994-02-01
1998-05-26
Harvey, Jack B.
Multiplex communications
Wide area network
Packet switching
39518319, 395408, 39518216, 370402, H04J 600, H04L 1200
Patent
active
057580537
ABSTRACT:
Parallel processors communicate with each other over a network by transmitting messages that include destination processor information. A message controller for each processor in the network receives the messages and checks for faults in the message, particularly in the destination processor number contained in a first word of the message. If a fault occurs in the destination processor number, then the faulty message is transmitted to an appropriate processor for handling the fault. In this way the network operation is not suspended because of the fault and the message is not left in the network as a result of the error occurring in the destination processor number. The processor to which the faulty message is directed is determined by a substitute destination processor number contained in the message or is predetermined and set in another way, such as by a service processor. To recover from the fault, the processor receiving the faulty message can request that the message be retransmitted or the error can be corrected using an ECC, for example. If the faulty message cannot be retransmitted, then the processor or the host processor can request that the job to which the faulty message pertains be canceled by all of the processors executing that job without affecting the simultaneous execution of other jobs by the same processors.
REFERENCES:
patent: 4166929 (1979-09-01), Sheibam
patent: 4195351 (1980-03-01), Barner
patent: 4281380 (1981-07-01), DeMuga et al.
patent: 4412281 (1983-10-01), Works
patent: 4417334 (1983-11-01), Gunderson et al.
patent: 4527237 (1985-07-01), Frieder
patent: 4598400 (1986-07-01), Hillis
patent: 4598404 (1986-07-01), Perry et al.
patent: 4663706 (1987-05-01), Allen et al.
patent: 4667287 (1987-05-01), Allen et al.
patent: 4677191 (1987-06-01), Carter et al.
patent: 4679189 (1987-07-01), Olson
patent: 5036518 (1991-07-01), Tsung
patent: 5065308 (1991-11-01), Evans
patent: 5115499 (1992-05-01), Stilz et al.
patent: 5126999 (1992-06-01), Munter et al.
patent: 5129077 (1992-07-01), Hillis
patent: 5166674 (1992-11-01), Baum et al.
patent: 5181017 (1993-01-01), Frey
patent: 5182750 (1993-01-01), Bales et al.
patent: 5239654 (1993-08-01), Ino-Simmons
patent: 5251299 (1993-10-01), Masuda
patent: 5271014 (1993-12-01), Bruck
patent: 5280474 (1994-01-01), Nickolls
patent: 5301273 (1994-04-01), Konishi
patent: 5301322 (1994-04-01), Hamanaka
patent: 5305462 (1994-04-01), Grondalski
patent: 5313408 (1994-05-01), Goto
patent: 5321813 (1994-06-01), McMillen
patent: 5369695 (1994-11-01), Chakravarti et al.
patent: 5428799 (1995-06-01), Woods et al.
Computer Systems Design, (Sanpo KK), pp. 216-218.
Routing Controller of Cellular Array Processor CAP-II, by T. Horie et al, The Information Processing Society of Japan Research Report, vol. 90, No. 60, pp. 223-228.
Broadcast-Network of Highly Parallel Processor CAP-II, by S. Kato et al, The Information Processing Society of Japan Research Report, vol. 90, No. 60, pp. 229-234.
Fujii Hiroaki
Higuchi Tatsuo
Inagaki Yasuhiro
Nakagoshi Junji
Obara Kiyohiro
Harvey Jack B.
Hitachi , Ltd.
Hitachi ULSI Engineering Corp.
Myers Paul R.
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