Data processing: measuring – calibrating – or testing – Measurement system – Performance or efficiency evaluation
Reexamination Certificate
1999-12-30
2002-12-10
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system
Performance or efficiency evaluation
C702S094000, C702S117000, C702S179000, C702S181000
Reexamination Certificate
active
06493654
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fault distribution analyzing system which analyzes a distribution of fault elements of a semiconductor integrated circuit in which circuit elements are arranged regularly.
2. Description of the Related Art
When a semiconductor integrated circuit has regularly arranged circuit elements and a distribution of fault circuit elements contained in the semiconductor integrated circuit is analyzed, the distribution of fault elements can be visually grasped if the positions of the fault elements are recorded. For example, when the circuit elements are divided into blocks and all of the circuit elements contained in one of the blocks are in failure, the block can be determined to be fault. When two adjacent circuit elements are in failure, the 2-bit pair can be determined to be in failure. Also, when one circuit element is independently in failure, the bit can be determined to be in failure. Moreover, when the neighbor elements are in failure massively, a bit group can be determined to be in failure.
The analysis of the distribution of fault elements is called a bit map analysis. The analysis is especially effective when the distribution of fault elements contained in a semiconductor integrated circuit such as a memory LSI or a memory mounting type logic LSI is analyzed. However, the number of elements contained in one semiconductor integrated circuit reaches 10,000,000 or more with the high integration of the semiconductor integrated circuit in recent years. For this reason, it is difficult for an operator to carry out the whole analysis of the distribution of fault elements based on the bit map analysis. Therefore, the technique for automatically analyzing the distribution of fault elements contained in the semiconductor integrated circuit is proposed in Japanese Laid Open Patent Application (JP-A-showa 61-23327) and Japanese Laid Open Patent Application (JP-A-Heisei 1-216278).
However, there are the following problems in the above-mentioned conventional examples of fault distribution analyzing apparatus.
First, it is difficult to determine whether fault elements distributed in a low density in a wide area over the whole semiconductor integrated circuit shows an irregular distribution or is contained in a regular distribution. Generally, when an analysis technical expert analyzes the distribution of fault elements contained in the semiconductor integrated circuit, the analysis technical expert observes the whole distribution at a low magnification and determines an area with a high fault element density. Then, the analysis technical expert observes the determined area at a high magnification and determines a correct position of the fault element and the regularity of the distribution of fault elements. However, when the fault elements are distributed in a low density in the wide area, the observation area at the high magnification gets wide. Therefore, the analysis by the analysis technical expert is difficult actually.
Second, it is difficult to find the period of the regularity, even when the regularity is discovered in the distribution of fault elements. The reason is that even if a position coordinate frequency distribution of fault elements is determined, the position coordinate range is wide so that the number of fault elements for position coordinate is 1 or a few. Also, this is because the distribution of the fault elements is low in density and is wide in area. In this way, it is difficult to correctly determine the period of the distributions of fault elements.
Third, there is another problem that the distribution of fault elements cannot be stored in the storage and correctly searched by a computer. That is, when the position coordinate of each fault element is to be searched, the number of fault element increases so that the data to be stored has become enormous in case of a semiconductor integrated circuit of a high integration. For this reason, because a storage unit had been saturated at a short time, the conventional fault distribution analyzing apparatus cannot be used in practical use.
On the other hand, a system searching the ratio of the number of fault elements and all the elements is known. However, in this system, a spatial distribution of fault elements cannot be represented, because the system does not contain the data indicative of the position coordinate of the fault element.
Moreover, a system is known which uses a histogram in which the number of fault elements is counted in accordance with the position coordinate. However, there are not distributions in which histograms are completely coincident with each other. Also, the pattern of the histogram becomes different in accordance with the increase of elements in a semiconductor integrated circuit. Therefore, it is difficult to search the histogram having the same pattern.
In conjunction with the above description, method of manufacturing an integrated circuit is disclosed in Japanese Examined Patent application (JP-B-Heisei 5-77178). This reference is directed to a method of manufacturing an integrated circuit which sometimes possibly contains any fault on a manufacturing process. The fault cannot be visually detected or requires an excessive long visual test for the detection. In this reference, a data base is produced to show a response which is caused by a specific fault of a type in response to a series of electric test signals. The series of electric test signals are applied to a manufactured integrated circuit. When any fault is detected, the manufacturing condition is examined so as to clearly specify the fault. Thus, the fault is avoided.
Also, a fault analyzing system of a semiconductor circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-221156). In this reference, the fault analyzing system (101) carries out analysis based on a data obtained through an alien substance test (102) and an outward appearance test (103) in a manufacturing process (111), a data obtained through a final wafer test (112) and a data obtained through a fail bit (FB) analysis system (105). The fail bit analysis system (105) extracts a fault position and a fault inducing position from a distribution of fail bits, using the data obtained through the final wafer test (112) and an LSI design data (107). Then, the fail bit analysis system (105) refers to a fault cause now-how data (108) to carry out estimation (113) of a fault cause. An observing unit (109) observes the fault position and the fault inducing position transferred from the fail bit analysis system (105) to specify the fault cause and a fault process. An analysis unit (110) carries out analysis of composition of an alien substance detected by the observing unit (109) to specify the fault cause and the fault process.
Also, a method of detecting and estimating a dot pattern is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-270012). In this reference, a dot pattern is spatially and discretely in a multi-dimensional coordinate system. Each of dots of the pattern takes either of two identifiable states. A measuring unit records a coordinate value and the state value of each dot of the dot pattern. A memory of a computer stores data corresponding to the coordinate value and state value of each dot. Coordinate counters are determined based on the stored data. A n-dimensional vector composed of components formed of the values of the determined coordinate counters is inputted to a neuron circuit network. The neuron circuit network compare the inputted vector and a reference vector corresponding to a reference dot pattern to calculate an output vector. A classification data of the measured dot pattern is outputted based on the output vector.
Also, a pattern test method is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-89931). In this reference, a concerned point (101) and comparison points (102
a
to 102
d
) distanced from the concerned point by a repetition pitch are cross-compared to extract comparison points having any dif
Hoff Marc S.
NEC Corporation
Suarez Felix
Young & Thompson
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