Fault detection signal transmission system

Details Fault detection signal transmission system Fault detection signal transmission system

1987-10-20

1989-10-24

Fleming, Michael R.

Excavating

371 3, G06F 1110

Patent

active

048766860

ABSTRACT:
A digital signal transmission system includes a transmit terminal which as an input interface circuit, a synchronous conversion circuit, a synchronous conversion circuit, a parity check circuit, a multiplex circuit for multiplexing a synchronized input signal with at least a parity check signal, a transmitter and antenna. A fault detector circuit of the transmit terminal detects faults in the input interface stage. The outputs of the fault detector circuit and the parity check circuit are input to a parity check signal output circuit which operates to invert the logical state of the output of the parity check circuit when a fault is detected. A digital signal reception system includes a receive terminal, which has a demultiplex circuit, a frame synchronization circuit, a parity check circuit, a synchronous conversion circuit, an output inface circuit, a receiver and antenna. The transmitted parity check signal is recovered from the demultiplex circuit. The receive terminal parity check circuit determines the parity signal from the received signal. A receive terminal parity check signal comparison circuit compares the determined parity signal with the recovered parity check signal. A fault in the transmit terminal input stage will be recognized at the receive terminal as a non-coincidence output from the comparison circuit.

REFERENCES:
patent: 4107649 (1978-08-01), Kurihara
patent: 4429391 (1984-01-01), Lee
patent: 4670876 (1987-06-01), Kirk
patent: 4682334 (1987-07-01), Le Mouel
patent: 4727548 (1988-02-01), Dickey
patent: 4744092 (1988-05-01), Betts

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