Fault detection process and system for a time-division switching

Details Fault detection process and system for a time-division switching Fault detection process and system for a time-division switching

1974-11-06

1976-02-10

Atkinson, Charles E.

Registers

Transfer mechanism

Traveling pawl

179 18J, G06F 1100

Patent

active

039379353

ABSTRACT:
A fault detection process and system is disclosed for large multistage time division-space division-time division switching networks. In the input time-division switch an origin bit is simultaneously transmitted with each sample to the related output channel of the output time division switch. The origin bit is produced by modulating a selected bit of the input channel address by an associated sample parity bit. In the output switch the modulated origin bit is demodulated by the received sample parity bit. This demodulated origin bit is compared with the corresponding bit of the input channel address which has been stored in a memory of the output switch under control of the network computer unit. In addition, means are provided for taking into account input delay, transmission delay and output delay.

REFERENCES:
patent: 3403229 (1968-09-01), Piereth
patent: 3449520 (1969-06-01), Hoschler et al.
patent: 3673340 (1972-06-01), Casella et al.
patent: 3689701 (1972-09-01), Vosonnet et al.
patent: 3755789 (1973-08-01), Collins
patent: 3760116 (1973-09-01), O'Toole

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