Fault detection in a LED bias circuit

Details Fault detection in a LED bias circuit Fault detection in a LED bias circuit

2001-03-27

2004-03-09

Sircus, Brian (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

C361S093700, C250S2140RC

Reexamination Certificate

active

06704183

ABSTRACT:

FIELD OF THE INVENTION
The invention is directed towards the field of light emitting diodes, particularly towards biasing circuits for light emitting diodes.
BACKGROUND
Products containing light emitting diodes (LED) which emit light in the visible or infrared range must conform to eye safety requirements, IEC 60825-1. If the optical flux that can impinge on a user's eye exceeds the standard, the device must be labeled an eye safety hazard, which is undesirable. This requirement applies not only during normal operation of the circuit but when single faults occur in the circuit.
FIG. 1
illustrates a prior art eye safety circuit. This simple circuit uses a fuse. When the bias current exceeds the eye safety requirement, the fuse blows.
FIG. 2
illustrates another prior art eye safety circuit. This circuit is a retriggerable transistor circuit that shunts current away from the LED when the current exceeds a design threshold.
The prior art circuits detect when the LED current is higher than some preset current. However, the circuit in
FIG. 1
cannot detect a fault in which the LED cathode is connected to GROUND, and the fuse cannot be readily integrated onto an integrated circuit. The circuit in
FIG. 2
can detect a fault where the LED cathode is shorted to Ground, but this circuit would be difficult to implement on a standard CMOS integrated circuit process.
SUMMARY
A bias circuit for light emitting diodes includes a switch connected to power. A light emitting diode connects to the switch output. Two bias current legs, electrically connected in parallel, interpose the light emitting diode and ground. A fault comparator is connected to the bias current legs and a logic OR gate. Four fault comparators can be implemented, each detecting a unique fault condition. The logic OR gate having an output connects to the input of the switch.
A first fault comparator has a negative input connected to the output of the bias current legs node VL, and a positive input receives a voltage signal VL−. This detects a short circuit from node VL to ground.
A second fault comparator has a positive input connected to one of the two bias current legs and a negative input connected to the other of the two bias current legs. This differentially compares the current between the two bias current legs.
To detect additional fault conditions, a bias resistor interposes the two bias current legs and ground. An amplifier has a positive input receiving a voltage reference signal, a negative input connected to the bias resistor, and an output connected to both bias current legs. A third comparator has a negative input receiving a voltage signal VREF+, having a positive input connected to the bias resistor. The third comparator detects when a high voltage on VB occurs. A fourth comparator has a negative input connected to the bias resistor and a positive input receiving a voltage signal VREF−. The fourth comparator detects when a low voltage on VB occurs.


REFERENCES:
patent: 4504776 (1985-03-01), Haville
patent: 4532472 (1985-07-01), Ishino
patent: 4940889 (1990-07-01), Ono et al.
patent: 5966110 (1999-10-01), Van Zalinge
patent: 6384804 (2002-05-01), Dodabalapur et al.

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