Fault detection arrangement for a digital conferencing system

Details Fault detection arrangement for a digital conferencing system Fault detection arrangement for a digital conferencing system

1984-05-07

1986-08-26

Fleming, Michael R.

Excavating

364738, 370 62, G06F 1110

Patent

active

046086935

ABSTRACT:
The disclosure relates to error/fault detection in signal processing systems such as those employed in a time division multiplex conferencer. The digital message samples (of the conferees) and the accompanying parity bits are delivered to a signal processor e.g., a binary arithmetic adder (10). The adder sums the message samples and this sum is coupled to a first parity tree (11), which in response thereto generates a first parity bit. The carries generated by the summing operation and coupled to a second parity tree (12) along with the message parity bits and the second parity tree generates a second parity bit therefrom. The first and second parity bits are compared (13) and if they differ a fault exists. Corrective action is taken immediately--the faulty conference "leg" is removed from the conference connection without affecting the remaining legs in the conference or any other conference.

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patent: 4304002 (1981-12-01), Hunt
patent: 4481624 (1984-11-01), Baranyai et al.
patent: 4523210 (1985-06-01), Kregness

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