Fault detection and redundancy management system

Details Fault detection and redundancy management system Fault detection and redundancy management system

1983-07-28

1987-01-06

Atkinson, Charles E.

Excavating

364131, 364186, 364187, 371 9, G06F 1516, G06F 1100

Patent

active

046341102

ABSTRACT:
A fault detection and redundancy management system for a dual redundancy based network architecture in which the principal control components (master units) are configured and programmed to repetitively carry out intra- and inter-unit performance tests as an a priori requirement for network command capability. These performance tests are carried out in a prescribed sequence to define the fault detection and reconfiguration procedure. The procedure is designed to preclude the cascading of faults. As a first step in this procedure, each processor in a master unit performs a thorough self-test of its own functional capability. Secondly, if a processor has determined that it has passed all of these internal procedures, it must then successfully inform a designated "chief" processor via an interprocessor handshake. This interprocessor handshake is effected by causing each processor in the master unit to set a flag in a shared memory during a prescribed time interval. These flags are read by the chief processor to determine whether to enable an associated bus controller for the next succeeding time interval, and once these flags have been read they are reset by the chief processor, as each processor is required to refresh the handshake flag during successive repetitive time intervals. If the chief processor determines that all units (including itself) are functional, it executes a handshake with a bus interface unit, so as to enable the bus interface unit to conduct I/O operations on the network bus. Failure to complete any portion of this procedure will cause the affected master unit to "off-line" with the result that the redundant master unit will take command of the network bus.

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R. S. Laughlin, The Galaxy/5: A Large Computer Composed of Multiple Microcomputers, 13th IEEE Computer Society Int. Conf., Sep. 7-10, 1976, pp. 90-94.

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