Fault correction apparatus for an address array of a store-in ca

Details Fault correction apparatus for an address array of a store-in ca Fault correction apparatus for an address array of a store-in ca

1996-10-28

1999-07-20

Chung, Phung M.

Excavating

711118, G06F 1100

Patent

active

059264845

ABSTRACT:
When a fault is detected in data read-out from an address array, a replacement controller registers the address in a replacement buffer. When this address is sent out from the replacement buffer, the address array is invalidated for the address by using an address register and a flush register. During the invalidation process, the processing of the request is suppressed by a pending register, and the request address is held in an address register until the invalidation is completed for use in retrying a cache indexing.

REFERENCES:
patent: 5564034 (1996-10-01), Miyake
patent: 5584002 (1996-12-01), Emma et al.
patent: 5845321 (1998-12-01), Ito et al.
J. Archibald et al.; "Cache Coherence Protocols: Evaluation Using a Multi-processor Simulation Model"; ACM Transactions on Computer Systems, vol. 4, No. 4, Nov. 1986, pp. 273-298.

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