Fault bypass for a processor associated scanner

Details Fault bypass for a processor associated scanner Fault bypass for a processor associated scanner

1975-06-02

1977-02-22

Stewart, David L.

179 18FG, H04M 312

Patent

active

040093484

ABSTRACT:
A processor equipment has an input highway connected to receive a multiplex signal from a number of peripheral devices such as multiplex units time division multiplxing telephone handsets. A counter is arranged to scan the devices for a processor interrupt signal and upon the occurrence of such a signal the counter is inhibited to enable the processor to take the appropriate action for the interrupting device, e.g. apply a dial tone. If one of the peripheral devices becomes faulty a store memorizes the fact that on a previous scan the device produced a non-valid interrupt signal and causes the address of a predetermined other peripheral device to be written into the counter at which scanning is to recommence.

REFERENCES:
patent: 3493683 (1970-02-01), Schlichte
patent: 3760113 (1973-09-01), Bouchet
patent: 3770899 (1963-11-01), Kobus
patent: 3787635 (1974-01-01), Kammerl
patent: 3821479 (1974-06-01), Campbell

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