Excavating
Patent
1981-05-04
1984-01-31
Atkinson, Charles E.
Excavating
G06F 1110
Patent
active
044293917
ABSTRACT:
A fault and error detection arrangement for detecting transmission and routing errors made by systems in which a central data transmitter/receiver (601, 610) bidirectionally intercommunicates with peripheral circuits (620) through an interconnection arrangement (604). The parity bits of certain data words transmitted by the central data transmitter (601) are intentionally inverted by a central parity inverter (602), in a known sequence. Data words transmitted by the central data transmitter (601) are routed by the interconnection arrangement (604) to the peripheral circuits (620) where parity is checked by a peripheral parity checker (621) and a parity invert signal is generated when an inverted parity data word is found. A peripheral parity inverter (623) included in each peripheral circuit (620) responds to the parity invert signals by inverting the parity bit of the next data word transmitted by a peripheral data transmitter (622) also included in each peripheral circuit (620). The data words transmitted by each peripheral circuit (620) are routed by the interconnection arrangement (604) to a central parity checker (610) in time-multiplexed channels. By the operation of the above arrangement, a known sequence of data words having inverted parity bits should be received by the central parity checker (610). An error signal generator (612) generates error signals when deviations from the expected sequence are detected.
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Atkinson Charles E.
Bell Telephone Laboratories Incorporated
Fleming Michael R.
Samples K. H.
Watland R. T.
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