Excavating
Patent
1991-11-13
1994-11-08
Atkinson, Charles E.
Excavating
371 103, G01R 3128
Patent
active
053633822
ABSTRACT:
An apparatus for analyzing faults in a memory having a redundancy circuit, includes an algorithmic pattern generator which generates address signals to select a memory cell of a memory under test and data which is written to a selected memory cell, a comparison circuit for performing a read operation after data has been written to a selected memory cell by address signals and comparing the data read and the data from the algorithmic pattern generator to determine whether or not it is in agreement and if it is not in agreement generating a fault signal that indicates that the memory cell is faulty, a fault analysis memory having a number of memory cells, and an address allocation circuit which receives address signals from the algorithmic pattern generator and performs address allocation for the fault analysis memory so that a number of memory cells of the memory under test correspond, based on a predetermined rule, to a single memory cell of the fault analysis memory.
REFERENCES:
patent: 4460997 (1984-07-01), Harns
patent: 4627053 (1986-12-01), Yamaki et al.
patent: 4627063 (1986-12-01), Yamaki et al.
patent: 4628509 (1986-12-01), Kawaguchi
Atkinson Charles E.
Kabushiki Kaisha Toshiba
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