Fault alignment exclusion method to prevent realignment of previ

Details Fault alignment exclusion method to prevent realignment of previ Fault alignment exclusion method to prevent realignment of previ

1982-06-16

1984-06-05

Atkinson, Charles E.

Excavating

371 38, 365200, G06F 1110

Patent

active

044532482

ABSTRACT:
A method is disclosed for insuring that two semiconductor chips which have a 1-bit defect at the same chip address are not paired at any memory address by a fault alignment exclusion mechanism (FAEM) which functions to position chips having defects at different memory addresses. The FAEM employs an error map to determine which chips must be realigned in their respective columns and an address permute vector functions to effectively change the physical address of the chip in the column to a logical address. The two permute vectors for the two columns contributing to any uncorrectable error are "exclusive-ORed" and the result stored in a second map along with an identification of the chip columns. Any time in the future that a new permute vector is proposed for assignment to any column of chips, the changed permute vector is exclusive-ORed with the permute vectors currently assigned to all other columns of the memory to see if any such combination produces a result forbidden by the forbidden result table. If no such forbidden result is found, the proposed permute vector can be assigned with the assurance that no pair of chips previously found to produce aligned faults will align now in any row of the memory. If any forbidden result is found, the proposed permute vector is discarded and a new one proposed.

REFERENCES:
patent: 3644902 (1972-02-01), Beausoleil
patent: 3897626 (1975-08-01), Beausoleil
patent: 4291389 (1981-09-01), Toth
Beausoleil, Maintenance for Memory with Error Correction, IBM Technical Disclosure Bulletin, vol. 11, No. 12, May 1969, pp. 1692-1693.
Chen, Fault Dispersion in Computer Memories, IBM Technical Disclosure Bulletin, vol. 25, No. 11A, Apr. 1983, pp. 5836-5838.
Ryan, Fault Realignment Through Grouping of Compatible Faulty Memory Chips, IBM Tech. Discl. Bulletin, vol. 26, No. 6, Nov. 1983, pp. 2753-2754.

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