Fault alignment control system and circuits

Details Fault alignment control system and circuits Fault alignment control system and circuits

1983-03-24

1985-08-06

Fleming, Michael R.

Excavating

365200, G11C 1140, G06F 1104

Patent

active

045340293

ABSTRACT:
This permutation circuit can be considered to be a multi-bit adder without a carry. In one embodiment it takes the form of m address bits being fed to m+y 2-way exclusive OR gates with m+y permutation bits to generate m+y input bits accessing a decoder with 2.sup.m output positions. In another embodiment the decoder takes the form an m bit adder with which adds m address bits to m permutation bits to generate m bit actual address. Multiple decoders of both types may be joined together in various combinations to generate higher order addresses. Also, k full-adder of less than m bits can also be used in similar fashion as m+y Exor gates to provide shift rotate capability within a desired block of 2.sup.y rows.

REFERENCES:
patent: 4047163 (1977-09-01), Choate
patent: 4051354 (1977-09-01), Choate
patent: 4051460 (1977-09-01), Yamada et al.
patent: 4191996 (1980-03-01), Chesley
patent: 4355376 (1982-10-01), Gould
patent: 4389715 (1983-06-01), Eaton et al.
patent: 4441170 (1984-04-01), Folmsbee et al.
patent: 4450559 (1984-05-01), Bond et al.
patent: 4459685 (1984-07-01), Sud et al.

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