Fast word line decoder for memory devices

Details Fast word line decoder for memory devices Fast word line decoder for memory devices

1995-09-13

1997-02-18

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365194, 365203, 365204, G11C 700, G11C 800

Patent

active

056047126

ABSTRACT:
A word line decoder gate including a plurality of parallel-coupled devices coupled to a common node for receiving and decoding an address upon assertion of a clock signal, where each parallel device receives a corresponding address signal or its inverted counterpart depending upon the particular address being decoded. A precharge device is coupled to the common node for keeping it at a first voltage level until the clock signal is asserted, and two series coupled charge devices are coupled between a source voltage and the common node, which charge devices attempt to charge the common node to a second voltage level during a time period while the clock signal is asserted and a delayed clock signal remains deasserted. A delay device receives the clock signal and asserts the delayed clock signal. However, any one or more of the parallel devices, if activated, provides a current path from said common node to override the two charge devices to keep the common node substantially at the first voltage level. Since decoding is performed in parallel, the present invention is easily extendible to as many address inputs as desired without any loss in performance. In the preferred embodiment, the parallel-coupled devices are discharge devices for keeping the common node discharged. Also in the preferred embodiment, a charge sustaining circuit is preferably coupled between the common node and the source voltage for reducing the effects of stray capacitance.

REFERENCES:
patent: 4514829 (1985-04-01), Chao
patent: 4774421 (1988-09-01), Hartmann et al.
patent: 5022010 (1991-06-01), Chan
patent: 5051959 (1991-09-01), Nakano et al.
patent: 5391941 (1995-02-01), Landry

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