Fast wakeup biasing circuit for analog-to-digital converter

Details Fast wakeup biasing circuit for analog-to-digital converter Fast wakeup biasing circuit for analog-to-digital converter

1997-10-02

1999-06-22

Hoff, Marc S.

Coded data generation or conversion

Analog to or from digital conversion

With particular solid state devices

341155, H03M 100

Patent

active

059146818

ABSTRACT:
Power control circuitry is provided in an analog-to-digital converter (1) having a CDAC array (2) coupled to an analog input signal, a comparator (3), and a successive approximation register circuit (5). The power control circuitry includes a bias control circuit (4) responsive to a powerdown signal and associated wakeup signal to produce a bias control signal (V.sub.BIAS). The bias control circuit includes a controllable current mirror circuit (10) which produces a first voltage (V.sub.C) on a first conductor (13) when the powerdown signal is at a first level to allow operation of the comparator in conjunction with the CDAC array and the successive approximation register circuit. The bias control circuit also includes a wakeup circuit (20) which precharges the first conductor (13) to a predetermined bias voltage (V.sub.C ') that is close in value to the first voltage (V.sub.C) in response to occurrence of the first level of the powerdown signal. The bias control signal V.sub.BIAS is produced and equal to the first voltage V.sub.C.

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