Fast updating peak detector circuit

Details Fast updating peak detector circuit Fast updating peak detector circuit

1981-01-22

1983-02-08

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307353, 328151, H03K 5153, G11C 2702, G01R 1904

Patent

active

043731414

ABSTRACT:
A peak detector circuit (10) is disclosed wherein an input signal is full-wave rectified by a circuit (14) and the rectified signal is provided simultaneously to peak detect, hold and dump circuits (18), (20). Each of the peak detect, hold and dump circuits is discharged at the start of periodic intervals with a phase offset between the intervals for the two circuits. The peak signals are discharged at essentially the start of the interval followed by rapid charging of the peak signal to the peak amplitude of the rectified input signal. The later portions of each of the intervals of the peak signals produced by the peak detect, hold and dump circuits (18) and (20) are transmitted alternately through a multiplexer circuit (24). The resulting output signal is transmitted through a high impedance buffer amplifier (30) to an output terminal (32) of peak detector circuit (10). The timing of the operation of multiplexer (24) serves to remove the discharge and charge transitions of the peak signals from the peak detected output signal.

REFERENCES:
patent: 3659211 (1972-04-01), Norton
patent: 3699948 (1972-10-01), Ota et al.
patent: 3710141 (1973-01-01), Zeiger
patent: 3835400 (1974-09-01), Briscoe
patent: 3969683 (1976-07-01), Fabricius
patent: 4031479 (1977-06-01), Thomas, Jr. et al.
patent: 4160175 (1979-07-01), Trout

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