Fast two-level dynamic address translation method and means

Details Fast two-level dynamic address translation method and means Fast two-level dynamic address translation method and means

1984-09-17

1987-09-22

Williams, Jr., Archie E.

Boots, shoes, and leggings

G06F 1210

Patent

active

046959505

ABSTRACT:
A unique high-speed hardware arrangement for generating double-level address translations in combination a translation look-aside buffer (TLB) structure that can store and lookup intermediate translations during a double-level translation. The hardware proceeds to the completion of a double-level translation without having to backup its operation, although an intermediate TLB miss is encountered, without danger of CPU deadlock occurring. The hardware arrangement also performs all single-level address translations required by the system.

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