Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Patent
1997-04-25
1998-10-20
Gaffin, Jeffrey A.
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
361111, 257356, H02H 322
Patent
active
058256008
ABSTRACT:
An apparatus for protecting an integrated circuit against damage from electrostatic discharge (ESD) includes an ESD bus that is connected to multiple input pads through a respective diode. The ESD bus--the node to be protected--is coupled to the negative power supply bus (V.sub.ss) by a FET-triggered SCR circuit. In particular, the SCR circuit includes, equivalently, a PNP bipolar transistor, and an NPN bipolar transistor interconnected so that each transistor receives base current from the collector terminal of the other. A field effect transistor (FET) is configured to trigger the SCR into conduction, to thereby provide a low-impedance path to safely shunt ESD charge. The drain terminal of the FET is connected to an intermediate node of a resistance between the ESD bus, and the PNP emitter terminal. ESD charge on an input pad of the integrated circuit forward biases the respective diodes, and charges the ESD bus. When the voltage on the ESD bus reaches a predetermined threshold voltage, the FET drain region breaks down, and triggers the SCR circuit into conduction to shunt the charge on the ESD bus to V.sub.ss. The voltage drop occasioned by current flowing from the ESD bus to the intermediate node at the onset of the FET drain breakdown hastens the turn-on of the SCR, thus improving the response time for handling fast ESD events, such as those in accordance with the Charged Device Model (CDM).
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Cypress Semiconductor Corp.
Gaffin Jeffrey A.
Sherry Michael J.
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