Fast tag compare and bank select in set associative cache

Details Fast tag compare and bank select in set associative cache Fast tag compare and bank select in set associative cache

1991-11-19

1994-10-04

Dixon, Joseph L.

Boots, shoes, and leggings

395400, 364DIG1, 3642461, 3642464, 3642484, 364955, G06F 1208

Patent

active

053534247

ABSTRACT:
A tag comparator and bank selector for a set-associative cache in a computer system operates in a minimum time so that a cache hit or miss signal is generated early in a memory cycle. The data memory of the cache has two (or more) banks, with a tag store for each bank, and the two banks are accessed separately and in parallel using the index (low order address bits) while the tag translation is in progress. Two bit-by-bit tag compares are performed, one for each tag store, producing two multibit match indications, one bit for each tag bit in each tag store. These two match indications are applied to two separate dynamic NOR gates, and the two outputs applied to a logic circuit to detect a hit and generate a bank-select output. There are four possible outcomes from the compare operation: both banks miss, left bank hits, right bank hits, and both banks hit. The later condition indicates a possible ambiguity, and neither data item should be used, so a miss is signalled. The comparator is in large part self-timed using a flow-through design, as distinguished from being enabled on clock edges. Delay elements in the bank select logic allow the banks to be timed against each other, and current limiters are employed to equalize the timing of miss signals, regardless of the number of match lines switching high (which is data dependent). An address producing 19-of-20 match bits will result in a NOR gate output of about the same timing as an address producing no match bits, even though the former will turn on only one transistor to discharge the precharged output node of the NOR gate, whereas the later will turn on twenty paths for discharge. Although a two-way set associative cache is shown herein as an example embodiment, one of the features of the invention is that higher levels of associativity, e.g., four-way and eight-way, are equally well accommodated.

REFERENCES:
patent: 4783736 (1988-11-01), Ziegler et al.
patent: 4914577 (1990-04-01), Stewart et al.
patent: 4953073 (1990-08-01), Moussouris et al.
patent: 5014195 (1991-05-01), Farrell et al.
patent: 5148536 (1992-09-01), Witek et al.
patent: 5210843 (1993-05-01), Ayers
O'Connor et al., "Modular Embedded Cache Memories for a 326 Pipeline RISC Microprossor", ISSCC 87, Feb. 27, 1987, pp. 256-257.
Suzuki et al, "A 19ns Memory", ISSCC 87, Feb. 26, '87, pp. 134-135 and 368.
Ooi et al, "Fail-Soft Circuit Design in a Cache Memory Control LSI", ISSCC 87, Feb. '87, pp. 103-104 and 91-92.
Nogami et al, "A 0.5W 64kB Snoopy Cache Memory with Flexible Expandability", ISSCC 91, Feb. 15, '91, pp. 266-267 and 327.
Watanabe, "An 8Kbyte Intelligent Cache Memory", ISSCC 87, Feb. 27, '87, pp. 266-267.

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