Fast static CMOS adder

Details Fast static CMOS adder Fast static CMOS adder

1995-06-06

1996-11-26

Mai, Tan V.

Boots, shoes, and leggings

364736, G06F 750, G06F 738

Patent

active

055792545

ABSTRACT:
An N-bit conditional sum adder comprised of a number of 2-bit adders coupled in series. The 2-bit adders have a sum generation circuit which computes two sum bits from two 2-bit inputs. Each sum bit is processed by a maximum of two multiplexers in series for factoring any carry-ins from preceding 2-bit adders, regardless of the total number of N bits to be added. A carry generation circuit generates two carry signals. The appropriate carry signal is selected for propagation by a multiplexer comprised of a number of p-n passgates. The two carry signals plus their complements are first buffered before being input to the multiplexer. The multiplexer outputs the appropriate carry signal and its complement to be input to a succeeding 2-bit adder and for controlling a succeeding multiplexer selection.

REFERENCES:
patent: 4707800 (1987-11-01), Montrone et al.
patent: 5047976 (1991-09-01), Goto et al.

Affiliated with

Also associated with

Rating

Fast static CMOS adder does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fast static CMOS adder, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fast static CMOS adder will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1978163