Fast start-up processor clock generation method and system

Details Fast start-up processor clock generation method and system Fast start-up processor clock generation method and system

1997-07-28

1999-10-05

Wambach, Margaret R.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327142, 327147, 327151, 327160, 327294, 327299, H03K 104

Patent

active

059630680

ABSTRACT:
A PLL based clock generation circuit that enables processor execution during phase locking is provided. A PLL (310) generates a PLL clock output to a divider (330), which divides the PLL clock at a system clock output. PLL (310) outputs a frequency lock signal upon acquiring a desired output frequency that initiates a counter (320) and enables execution in a CPU (350) being clocked by the system clock. CPU (350) is thereby enabled to execute during phase locking at a divided frequency without risk of frequency overshoot induced failures. A phase lock signal, indicating PLL (310) has achieved phase lock, output by counter (320) is logically combined (340) with a signal output from CPU (350) requesting maximum frequency operation. The combined signal selects divider (330) to enable a maximum frequency system clock, thereby enabling CPU (350) to execute at maximum frequency when the PLL (310) is safely phase locked.

REFERENCES:
patent: 4748559 (1988-05-01), Smith et al.
patent: 4758945 (1988-07-01), Remedi
patent: 5410582 (1995-04-01), Sato
patent: 5694308 (1997-12-01), Cave

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