Fast single precision floating point accumulator using base...

Details Fast single precision floating point accumulator using base... Fast single precision floating point accumulator using base...

2006-01-17

2006-01-17

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06988119

ABSTRACT:
The proposed fast single precision floating point accumulator of the present invention uses base 32 computation in an attempt to completely remove the need for a costly 8-bit subtractor in the exponent path as is commonly found in conventional designs. It also replaces the expensive variable shifter in the mantissa path with a constant shifter which significantly reduces the cost of the present invention relative to earlier floating point accumulators. The variable shifter required for base 2 to base 32 conversion has been moved outside the accumulator loop. This approach allows comparison of the two input exponents using a comparator. The mantissas are shifted by constant amount to bring them into partial alignment. They are then added or the appropriate mantissa is chosen as the result. The input stream to the accumulator does not need to be cumulative.

REFERENCES:
patent: 4994996 (1991-02-01), Fossum et al.
patent: 5687106 (1997-11-01), Schwarz et al.
patent: 5889980 (1999-03-01), Smith, Jr.
patent: 2002/0095451 (2002-07-01), Krygowski et al.
A. Beaumont-Smith, et al., “Reduced Latency IEEE Floating-Point Standard Adder Architectures” IEEE, 1999.
Erdem Hokenek, et al., “Second-Generation RISC Floating Point with Multiply-Add Fused”, IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 1990, pp. 1207-1213.
Fayez Elguibaly, “A Fast Parallel Multiplier-Accumulator Using the Modified Booth Algorithm”, IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, vol. 47, No. 9, Sep. 2000, pp 902-908.
G. Panneerselvam and B. nowrouzian, “Multiply-Add Fused RISC Architectures for DSP Applications”, IEEE Pac Rim '93, pp 108-111.
Zhen Luo and Margaret Martonosi, “Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques” IEEE Transactions on Computers, vol. 49, No. 3, Mar. 2000, pp 208-218.

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