Fast, simultaneous multi-processor system status communication i

Details Fast, simultaneous multi-processor system status communication i Fast, simultaneous multi-processor system status communication i

1990-08-31

1993-04-13

Fleming, Michael R.

Boots, shoes, and leggings

395200, 395425, 364228, 3642283, 3642281, 3642222, 364284, 364229, 3642646, 364DIG1, G06F 1300, G06F 1516

Patent

active

052029980

ABSTRACT:
Each processor in a multi-processor system has an associated interface circuit which comprises a register for storing a flag bit status and evaluation logic for comparing the stored flag bit status with an update status from the associated processor. The comparison of the update status with the stored status results in the generation of an associated change status which identifies the changed flag bits. Each interface circuit receives the change status from all other interface circuits. The generated change status is combined with the received change status to determine the combined changed flag bits from all processors. The resultant combined changed flag bits are compared with the original flag bit status and an updated flag bit status is generated therefrom. All processors in the multi-processor system can communicate their respective status changes simultaneously without following a predetermined protocol.

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R. C. Cash et al., Multi-Processor Communications Interface, IBM TDB, Sep. 1988, pp. 467-469.

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