Fast sign extend for multiplier array sums and carrys

Details Fast sign extend for multiplier array sums and carrys Fast sign extend for multiplier array sums and carrys

1995-09-11

1998-10-20

Elmore, Reba I.

Boots, shoes, and leggings

G06F 752

Patent

active

058256792

ABSTRACT:
A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.

REFERENCES:
patent: 4748582 (1988-05-01), New et al.
patent: 5119325 (1992-06-01), Viot et al.
patent: 5251167 (1993-10-01), Simmonds et al.
patent: 5262976 (1993-11-01), Young et al.
patent: 5426599 (1995-06-01), Machida
patent: 5506799 (1996-04-01), Nakao

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