Fast shift amount decode for VMX shift and vperm instructions

Details Fast shift amount decode for VMX shift and vperm instructions Fast shift amount decode for VMX shift and vperm instructions

1998-06-25

2000-09-12

Eng, David Y.

Electrical computers and digital processing systems: processing

Byte-word rearranging, bit-field insertion or extraction,...

G06F 1300

Patent

active

061192244

ABSTRACT:
A multimedia facility within a processor employs a crossbar to perform operations requiring byte reordering. Prior to the cycle in which an instruction is executed, the instruction is checked to determine if the instruction is a predetermined type of instruction. If not, the operand which should contain encoded crossbar selects is filled with zeros before presentation to the crossbar select generation logic. If the instruction is one of the predetermined type of instructions, however, the real operand containing the encoded crossbar selects is presented to the crossbar select generation logic. As a result, only crossbar selects which designate byte 0 of the source operand as the source need to be qualified with a signal verifying the instruction being executed. The fanout of the qualification signal is thus reduced to an acceptable level, at which 1 cycle latency and 1 cycle throughput may be achieved.

REFERENCES:
patent: 4999808 (1991-03-01), Blabut
patent: 5524245 (1996-06-01), Zarrin et al.
patent: 5592684 (1997-01-01), Gaskins
patent: 5781923 (1998-07-01), Hunt
patent: 5819117 (1998-10-01), Hanson
patent: 5918075 (1999-06-01), Paysan

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