Fast settling fine stepping phase locked loops

Details Fast settling fine stepping phase locked loops Fast settling fine stepping phase locked loops

2001-03-07

2004-07-20

Tran, Pablo N. (Department: 2683)

Telecommunications

Receiver or analog modulated signal frequency converter

Local control of receiver operation

C455S258000, C455S259000, C455S265000, C455S266000, C331S017000, C331S025000

Reexamination Certificate

active

06766154

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to phase locked loops circuits, and, more particularly, to an improved active loop filter for a bandwidth switchable phase locked loop that is fast switching and fast settling with minimal electronic noise.
BACKGROUND
A phase-locked loop (“PLL”) is an electronic circuit that incorporates a feedback arrangement to maintain an output signal in a specific relationship with a reference signal. Phase locked loops are used in many kinds of electronics devices to control the frequency and/or phase of a signal. Devices applications for the PLL include tone decoders, demodulators of AM and FM signals, frequency multipliers, frequency synthesizer, pulse synchronizers of signals from noisy sources and regenerators of clean signals.
Typically, a phase locked-loop includes a phase detector, a loop filter and a voltage controlled oscillator (“VCO”). The phase detector compares two input frequencies, generating an output, the phase error signal, that is a measure of the phase difference between those frequencies. If the frequencies differ, the phase error signal is a periodic output at the difference frequency. In the PLL, a reference signal is applied to an input of a phase detector and the output of the VCO is fed back to another input of that phase detector, the feedback arrangement. The phase detector produces a phase error signal that represents the phase (or frequency) difference between the reference signal and the VCO output. After being filtered (and, optionally, amplified) in the loop filter, the filtered (and/or filtered and amplified phase error signal) is applied to the control input of the VCO as a control signal. The control signal causes the frequency of the VCO to deviate in the direction of the reference signal, little by little, while the PLL is settling. When the conditions are right, the VCO quickly shifts in frequency to “lock” on to the reference signal, maintaining a fixed phase with that reference signal. If the frequency of the reference signal is quickly changed in frequency, the foregoing procedure repeats until the PLL again locks to the reference signal.
A typical PLL has three operational modes: a free running mode, in which the reference signal is absent; a capture or acquisition mode in which an output signal from the VCO is different from the reference input signal and the VCO is in the process of continuously changing a phase of its output signal until the output signal maintains the same phase as the reference input signal; and a locked mode, in which the VCO output signal tracks and varies exactly with the phase of the reference input signal.
The speed at which the PLL attains the locked state depends in great part on the bandwidth of the loop filter. A loop filter that has a wide bandwidth is preferred for the capture or acquisition mode because with that filter the PLL has a faster acquisition time. That is, the PLL attains a steady state very quickly. That property is desirable in applications in which the PLL must be switched from one frequency of operation to another very rapidly, such as, as example, in a frequency and time division multiplexing system in which frequencies are stepped at intervals from one frequency to another. A drawback to the wide bandwidth is that wide bandwidth is accompanied by relatively high levels of electronic noise, such as jitter. A loop filter that has a narrow bandwidth is preferred for the locked mode of operation. The narrow bandwidth minimizes the generation of electronic noise, although with that filter the PLL tunes or locks to the reference frequency relatively slowly.
Others have recognized that it is possible to optimize the operation of a PLL by employing a loop filter with a bandwidth that can be changed, a switchable bandwidth. By switching the characteristic of the loop filter between a broad bandwidth and a narrow bandwidth as needed, the benefits of both bandwidths is achieved in the PLL. In a U.S. patent to Donohue, U.S. Pat. No. 6,064,273 (the '273 patent) a band pass filter circuit is described which incorporates a PLL. The PLL contains a loop filter that is of broad bandwidth during the acquisition mode of the PLL and is of narrow bandwidth during the locked mode. The change in characteristic is accomplished, for one, with a pair of oppositely poled diodes placed across a resistance in the loop filter. During the acquisition mode, depending on the polarity of the voltage, one of the diodes conducts and shunts the resistance, the effect of which is to produce a wide bandwidth for the loop filter. When the voltage across the diode drops below a defined level, which occurs after the PLL locks to the reference frequency, the diode no longer shunts the resistance. With the added resistance in the loop circuit, the loop circuit becomes narrower in bandwidth.
Although the loop filter in the PLL of the '273 patent is switchable, the switching time is not controlled. To switch between broad bandwidth and narrow bandwidth in the active loop filter of a PLL and maintain the switching time thereof to a minimum, the traditional approach has been to use two electronic switches, operated simultaneously, in an inverting loop filter arrangement. One electronic switch (RS), when operated to closed condition, raises the gain of the loop filter; and the second electronic switch (RF), when operated to closed condition, maintains the damping of the loop circuit.
The active loop filter of the foregoing PLL included an operational amplifier with the output of the amplifier serving as the output of the filter. The feedback network for the amplifier consists of a resistor and capacitor connected in series between the inverting (−) input and the output of the foregoing amplifier. The output of the phase detector was connected in series with a second resistor to the inverting input and the non-inverting (+) input was grounded.
The foregoing PLL is satisfactory and satisfies the requirements of many applications. Unfortunately, it inherently produces a higher level of phase/frequency perturbation, and, hence, is not satisfactory for some applications, such as the frequency synthesizer for a cell phone multiplexing system next described.
One application in which fast bandwidth switching and low electronic noise is required is found in cellular telephone systems. In one such cellular system a base station controls a large number of different active cell phones to enable cell phone voice and/or data traffic to be carried in the telephone system simultaneously. Briefly speaking, such simultaneous cell phone transmissions are made possible through use of a frequency and time division multiplexing system employed at the base station. The base station equipment assigns each active cell phone a specific carrier frequency. Using a frequency synthesizer, the base station multiplexing equipment then produces each of those assigned carrier frequencies individually in serial order for a very short interval, allowing the modulated carrier frequency signal from each cell phone to pass momentarily through transmission circuits into the base station equipment. The multiplexing system repeats the foregoing frequency switching periodically between frequencies at a very high rate, so high that the interruptions (eg. Divisions) are not discernable by the users of the cell phones. Typically, the frequency synthesizer in the foregoing multiplex system is required to frequency “hop” or “step” between the individual carrier frequencies in a time of about one to ten microseconds.
Not only must the foregoing frequency synthesizer change frequency almost instantaneously, the synthesizer must do so without generating significant phase/frequency perturbation as would cause interference with the telephone traffic. As one appreciates, abrupt changes in an electronic circuit typically produces spurious or transient signals until the electronic circuit recovers from the change. That is, the synthesizer must be “fast settling”. Such fast settling synthesizers have been implemented to date in the c

Affiliated with

Also associated with

Rating

Fast settling fine stepping phase locked loops does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fast settling fine stepping phase locked loops, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fast settling fine stepping phase locked loops will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3215593