Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression
Reexamination Certificate
2003-05-21
2004-08-31
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Unwanted signal suppression
Reexamination Certificate
active
06784727
ABSTRACT:
FIELD OF INVENTION
The present invention generally relates to circuits for signal alignment and, in particular, circuits for fast-settling signal alignment and DC offset removal.
BACKGROUND
In the processing a received signal, it is desirable to quickly settle the received signal in order to process the signal. However, an unintended DC offset component may have been introduced to the received signal from a variety of sources as the signal is transmitted in stream or processed by the circuitry. The resulting distorted signal would be difficult to decode, would cause further complications, and generates undesirable effects to the downstream circuitry. Thus, the removal of this undesirable DC offset component, along with the quickly settling of the received signal, becomes important issues in many applications.
For example, zero-intermediate-frequency (Zero-IF) architectures have become very popular in analog base band circuits for radio frequency (RF) receivers due to its lower requirements on channel select filters and amplifiers. This type of architecture demands that the received signal be processed at low frequencies with amplitudes that are very close to zero. Hence, the removal of undesirable DC offset generated by, for example, mismatch, local oscillator (LO) leakage, or self-mixing becomes a critical issue.
In the prior art, many transceivers use calibration techniques to remove the DC offset. Although calibration techniques can effectively remove DC offset caused by mismatch and LO leakage, DC offset caused by self-mixing of a strong interferer and other operation-dependent sources can not be easily predicted and canceled. Calibration techniques also considerably increase circuit complexity and require close collaboration between analog and digital receiver chips.
Another method for DC offset removal is the insertion of a simple RC filter, as is illustrated in
FIG. 1
, which utilizes a capacitor to block DC voltage level and a resistor to provide DC bias for the following circuits. Cut-off frequency of this RC circuit should be small enough to reduce attenuation of signal intensity and group delay and be large enough to be able to settle to near asymptotic state within a required time that is specified by the standard. For example, in the IEEE802.11 standards for wireless local area network (WLAN) applications, cut-off frequency of less than 10 KHz is desired. A naive implementation of this circuit with frequency this low would take hundreds of microseconds to settle. However, the standard also requires DC offset cancellation circuit to settle within a period of 800 nS, three orders of magnitude lower. Previous works by others have implemented switchable RC filters that can switch cut-off frequency from high to low in three or more discrete steps. This method cannot reliably settle because the discrete switching action itself will generate a DC offset depending on the signal levels at the input and at the output at the switching instant. The fundamental reason of switching-induced DC offset will be explained in more details later in this disclosure.
In analyzing a simple RC filter as illustrated in
FIG. 1
, a differential equation can be derived to describe the filter's behavior in the time domain.
C
ⅆ
(
V
out
-
V
in
)
ⅆ
t
=
-
V
out
R
(
1
)
With the initial condition
V
out
&RightBracketingBar;
t
=
0
=
V
0
(
2
)
The solution is
V
out
=
∫
0
t
p
(
t
′
)
ⅆ
V
in
(
t
′
)
ⅆ
t
′
ⅆ
t
′
+
V
0
p
(
t
)
,
p
(
t
)
=
ⅇ
∫
0
t
(
RC
)
-
1
ⅆ
t
′
(
3
)
Define cutoff frequency f
T
to be:
f
T
=
1
2
π
RC
(
4
)
Assume that at time t=t
0
, the cut-off frequency is changed from f
T
to f
T
′ and the input signal can be decomposed into
V
in
=
∑
n
=
0
m
A
n
ⅇ
j
(
ω
n
t
+
φ
n
)
(
5
)
If &ohgr;
T
is assumed to be constant, it can be derived that
V
out
=
∑
n
=
1
m
{
1
1
-
j
ω
T
ω
n
A
n
ⅇ
j
(
ω
n
t
+
φ
n
)
+
V
0
p
(
t
)
-
A
n
ⅇ
jφ
n
p
(
t
)
·
1
1
-
j
ω
T
ω
n
}
(
6
)
In Equation (6), it is evident that the output voltage consists of three components: the desired signal represented by the first term in the bracket; the decaying voltage caused by initial condition of output voltage; and the decaying term caused by the instantaneous input signal level at initial time. Equation (6) shows that frequency switching will introduce other DC offset voltages itself while removing DC offset changes from the input. This switching-induced DC offset is proportional to the input signal amplitude and depends on the signal level at the input and the output at the switching instant. One of the challenges here is to remove this DC offset voltage in a fast and efficient manner so that information can be extracted from the signal.
If the system is in steady state with cut-off frequency of
&ohgr;
T before it is switched to
&ohgr;
T′ at t=0, the output voltage is
&AutoLeftMatch;
V
out
=
∑
n
=
1
m
{
1
1
-
j
ω
T
′
ω
n
A
n
ⅇ
j
(
ω
n
t
+
φ
n
)
+
A
n
ⅇ
jφ
n
p
(
t
)
·
(
1
1
-
j
ω
T
′
ω
n
-
1
1
-
j
ω
T
ω
n
)
}
=
∑
n
=
1
m
{
1
1
-
j
ω
T
′
ω
n
A
n
ⅇ
j
(
ω
n
t
+
φ
n
)
+
A
n
ⅇ
jφ
n
p
(
t
)
·
(
j
(
ω
T
′
-
ω
T
)
/
ω
n
(
1
-
j
ω
T
′
ω
n
)
(
1
-
j
ω
T
ω
n
)
)
}
(
7
)
From Equation (7), it can observe in the second term on the right side that in the frequency switching schemes there is a DC offset that is roughly proportional to the difference of switched frequency. Equation (7) shows that to minimize switching induced DC offset, a smooth and continuous frequency change is highly desirable.
Based on the developed mathematical models, it is therefore desirable to have innovative circuits and methods for continuous frequency-switching to overcome the shortcoming of prior art technologies.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide circuits for DC offset removal with continuous frequency-switching.
It is another object of the present invention to provide continuous variable resistance control circuits for DC offset removal.
It is yet another object of the present invention to provide current controlled continuous, variable resistance control circuits for DC offset removal.
Briefly, a fast-settling DC offset removal circuit with continuous cutoff frequency switching is disclosed. In the preferred embodiment, the circuit is implemented using a pair of RC filters for receiving a differential signal pair and a continuous, variable resistance control circuit. The control circuit can be current-controlled or voltage controlled to provide fast settling of the received signal and the removal of the DC offset components. Additionally, by using a current-controlled variable resistance circuit, the cutoff frequency of the RC filter can be ramped from high to low in a continuous manner, thereby minimizing the generation of DC offsets.
An advantage of the present invention is that it provides circuits for DC offset removal with continuous frequency-switching.
Another advantage of the present invention is that it provides continuous variable resistance control circuits for DC offset removal.
Yet another advantage of the present invention is that it provides current controlled continuous, variable resistance control circuits for DC offset removal.
REFERENCES:
patent: 5208693 (1993-05-01), Arstein et al.
patent: 6583746 (2003-06-01), Tokioka
patent: 6611167 (2003-08-01), McMahon et al.
Peter M. Stroet, A Zero-IF Single Chip Transceiver for up to 22Mb/s QPSK 802.11b Wireless LAN. 2001 Digest of Technical Papers of IEEE International Solid-State Circuits Conference (ISSCC &
Cao Kanyu
Chao Chieh-Yuan
Chen Tung-Shan
Li Hongyu
Chang Emil
Hyperband Communication, Inc.
Law Offices of Emil Chang
Zweizig Jeffrey
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