Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2001-03-13
2004-03-30
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S217000, C327S219000
Reexamination Certificate
active
06714053
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is generally directed to compensating for circuit propagation delays in strobed comparators and, more specifically, to compensating for circuit propagation delays in strobed comparators that use regenerative latches.
BACKGROUND OF THE INVENTION
Integrated circuit designs often use strobed comparators to achieve extremely high gains. One limitation of strobed comparators is that the decision circuit outputs of the comparator become invalid once the comparator is in the reset phase. This problem is generally overcome by having a regenerative, or Set-Reset (SR), latch on the output of the decision circuit of the comparator to hold the output value during the reset phase.
Therefore, a strobed comparator now often comprises a decision circuit and an SR latch circuit. The output of the decision circuit is input to the SR latch circuit. The “strobe” signal is also referred to as the “latch” signal. When the latch signal is low, the decision circuit is in reset phase. When the latch signal goes high, the decision circuit makes a decision and outputs the decision to the SR latch. When the latch signal then goes low, the decision circuit is again in reset phase. However, the SR latch holds the value of the decision that the decision circuit made when the latch signal was high. The length of time of the “latch” phase and the length of time of the reset phase are determined by the level of the latch voltage.
SR latches usually have a delay between the first output (Q) changing state and the second complementary output (Qb) changing state. This can give rise to “runt pulses” which are output pulses that do not reach the prescribed voltage level for a logic family's defined state before the pulse retreats.
The delay between outputs can also cause incorrect transients when both outputs of the SR latch are being used in logic operations downstream. For example, in a pipelined analog-digital converter, the delay between the comparator switching and a stage entering hold state must be minimized in order to obtain and maintain increased speed. Furthermore, incorrect transients reduce the hold time even more as the operational amplifier in a residue stage has to overcome the initial incorrect decision. Therefore the propagation delay through the SR latch is the larger of the Q delay or the Qb delay. The analog to digital converter (ADC) must not go into a hold state until after this delay.
Latches that are used today generally have a gate delay between the outputs. One output, output Q, arrives at a certain time but the other output, output Qb, usually arrives later. Alternatively, output Qb arrives first and output Q arrives later. If the comparator is driving a digital to analog converter (DAC), it is important for both outputs to arrive at the same time. Delay for both output scenarios is usually about ten percent (10%) of the delay time of the entire comparator or the latch. Both outputs, Q and Qb, must be active before processing can take place. Because of the output delay inherent in currently available prior art latches, a prior art comparator is approximately ten percent (10%) slower than it would be if there were no output delay.
There is therefore a need in the art for an apparatus that will reduce the delay between outputs in an SR latch circuit in a strobed comparator.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide an apparatus for reducing the delay between outputs in a fast set reset (SR) latch circuit in a strobed comparator.
During the reset phase of the SR latch circuit, only one input to the SR latch circuit changes state while the other input to the SR latch circuit returns to its previous logic state. In the present invention, this information is provided to two transistors that then feed forward the decision circuit state change directly to the SR latch output that is likely to have an output signal delay. By transmitting the input state change to the output of the SR latch that will likely have an output signal delay, the output signals will arrive at the Q output terminal and at the Qb output terminal at the same time.
It is an object of the present invention to provide a fast SR latch that is capable of holding an output from a decision circuit to which the SR latch is coupled.
It is also an object of the present invention to provide a fast SR latch that is capable of determining the logic state of a first output and a second output of a decision circuit to which the SR latch is coupled.
It is an additional object of the present invention to provide a fast SR latch that is capable of sending a logic state of one of either a first output or a second output of a decision circuit to either a first feed forward transistor or a second feed forward transistor.
It is also an object of the present invention to provide a fast SR latch that is capable of utilizing a first feed forward transistor and a second feed forward transistor for controlling a first and second output of an SR latch.
It is also an object of the present invention to provide a fast SR latch that is capable of coordinating the timing of output signals of a strobed comparator.
It is also an object of the present invention to provide a fast SR latch that is capable of eliminating “runt pulses” in logic circuitry coupled to the output of a strobed comparator, where the runt pulses are caused by delays between a first output changing state and a second complementary output changing state.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.
REFERENCES:
patent: 4717838 (1988-01-01), Brehmer et al.
patent: 6060912 (2000-05-01), Opris et al.
patent: 6169533 (2001-01-01), Tse
patent: 6232810 (2001-05-01), Oklobdzija et al.
patent: 406177715 (1994-06-01), None
National Semiconductor Corporation
Nguyen Long
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