Fast semiconductor digital logic inverter gate

Details Fast semiconductor digital logic inverter gate Fast semiconductor digital logic inverter gate

1978-09-25

1980-12-16

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307213, 307237, 307303, H03K 1920, H03K 19177

Patent

active

042399815

ABSTRACT:
An extremely fast, highly regulated and nonresistive semiconductor digital logic inverter gate which is suitable for use as a fundamental building block in an uncommitted gate array includes an input conductor, at least one output conductor, a first current source providing a fixed current of a given magnitude to the input conductor, a second current source providing a current varying exponentially with input voltage to each output conductor, and a current control circuit operating in response to current flow through the input conductor to control the magnitude of current provided by the second source of current to each of the output conductors at a magnitude greater than the first magnitude or at a nonzero magnitude substantially less than the first magnitude. Subnanosecond time delays in switching between digital logic states are attained by constructing the logic gate as an integrated circuit from Schottky diodes which have very little transit time delay and bipolar transistors which are never biased into either saturation or cutoff. Capacitance charging time is minimized by utilizing a small difference in forward bias voltage drops across different kinds of Schottky diodes to clamp digital logic voltage swings at approximately 133 millivolts or less. Because of its exponential voltage current relationship this voltage differential applied across the base emitter terminals of a transistor utilized in the second current source is sufficient to provide current differentials greater than 100:1 for maintenance of a good noise margin.

REFERENCES:
patent: 3962590 (1976-06-01), Kane et al.
patent: 4009397 (1977-02-01), Mulder et al.
W. J. Nestork, "High-Speed Logic Circuit", IBM Technical Disclosure Bulletin, vol. 4, No. 8, Jan. 1962, pp. 41-42.
W. Mayeda, "Logical Circuit", IBM Technical Disclosure Bulletin, vol. 3, No. 10, Mar. 1961, p. 76.

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