Fast scan/set testable latch using two levels of series gating w

Details Fast scan/set testable latch using two levels of series gating w Fast scan/set testable latch using two levels of series gating w

1984-03-22

1986-12-09

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307272R, 307291, 307465, H03K 19086

Patent

active

046282173

ABSTRACT:
An economical circuit of n transistors and m resistors (n=4, m=1 for Emitter Coupled Logic (ECL); n=3, m=0 for Current Mode Logic (CML)) interconnects to a fast differential feedback latch of r transistors and s resistors (r=12, s=9 for ECl; r=7, s=3 for CML) using two levels of series gating and one current source in order to establish scan/set testability of such latch. An additional interconnected circuit of v transistors and w resistors (b=2, w-1 for ECL; v=1, w=0 for CML) further establishes either a reset or a set capability for such latch. The economical total scan/set testable latch of x transistors and y resistors (x=18, y=11 for ECL; x=11, y=3 for CML) exhibits an excellent delay-power product since a single current is selectively steered into one of four different paths, the remaining three of which paths are shut down. Use of but a single current source provides further economy of silicon implementation. All such economies are achieved by the trade-off that the scan/set testable latch does exhibit a higher than normal number of combinations of input signal conditions responsively to which the output signals will be indeterminate: some 9 out of a nominal 32 combinations of 5 input signals for which the output states of latches are often specified will produce undetermined signal outputs. Such 9 combinations are, however, essentially unused and never encountered when the scan/set testable latch is implemented and used, as is primarily intended, in gate array technology.

REFERENCES:
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patent: 4493077 (1985-01-01), Agrawal et al.
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Canova et al, "LSSD Compatible D-Function Latch", IBM TDB, vol. 25, No. 10, Mar., 1983, pp. 5196-5198.
Blumberg et al, "High-Speed Glitchless Cascade Latch with Set", IBM TDB, vol. 18, No. 5, Oct., 1975, pp. 1415-1416.
Berglund, "Level-Sensitive Scan Design Tests Chips, Boards, System", Electronics vol. 52, No. 6, Mar. 1979, pp. 108-110.

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