Fast sampling phase locked loop frequency synthesizer

Details Fast sampling phase locked loop frequency synthesizer Fast sampling phase locked loop frequency synthesizer

1981-09-28

1984-07-03

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 10, 331 17, H03L 718

Patent

active

044582145

ABSTRACT:
The output frequency of a phase locked loop frequency synthesizer is measured by a counter which counts whole output cycles and a timer providing a signal proportional to a fractional output cycle during a sampling period. The counter output is stored into a latch at each sampling period. Calculated frequency is generated by an accumulator which is incremented a selectable integer N at the completion of each sampling period. The accumulator output is divided into a first part relating to whole cycles and a second part relating to fractional cycles. An adder takes the difference of the latch stored number and the accumulator output first part. The resulting difference, with the accumulator output second part restored thereto, comprises a coarse error signal in digital form. The digital coarse error signal is converted to analog and applied as one input to a summer. A second input to the summer is provided by the timer signal after being scaled proportionately to N in a multiplying D/A converter. The summer output constitutes a refined error signal which is applied through a loop filter to regulate the output frequency of the phase locked voltage controlled oscillator.

REFERENCES:
patent: 3555446 (1971-01-01), Braymer
Bjerede, B. et al, "An Efficient Hardware Implementation For High Resolution Frequency Synthesis", Proceedings of the 30th Annual Symposium on Frequency Control, Atlantic City, N.J., Z-4, Jun. 1976, pp. 318-321.

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