Fast sample-and-hold peak detector circuit

Details Fast sample-and-hold peak detector circuit Fast sample-and-hold peak detector circuit

2003-06-24

2004-09-07

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

Reexamination Certificate

active

06788115

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to circuitry for detecting peak levels of signals and particularly fast sample-and-hold peak detectors for analyzing signals of generally arbitrary wave shape and form having a high precision, high slew-rate, very short retention, and a low distortion.
The invention is based on a priority application, EP 02360224.6, which is hereby incorporated by reference.
2. Background
Peak signal detectors are widely known and useful circuit devices. A peak detector may be used in an analog-to-digital signal converter, as a demodulator, or as a diagnostic tool.
Various circuit solutions have been suggested for providing peak signal indications. Among them are peak envelope detectors, sample-and-hold peak detector circuits and level sensing circuits. Known solutions have a wide variety of limitations and disadvantages, including limitations on large amplitude operating range and frequency range and inability to approach true peak level detection.
What is needed is a peak detector which approaches true peak detection over a wide frequency range with high precision, high slew-rate, very short retention, and a low distortion.
A technique of detecting an analog signal at high speed and converting it into a digital signal has recently been essential to networking and multimedia. There a sample-and-hold peak detector circuit is necessary for an analog-to-digital conversion. As one method of the sample-and-hold peak detector circuit, there is a combination of a high-speed switch circuit and a voltage holding capacitor, for catching analog signals sampled in a short time slot and holding their peak values.
For circuits processing digital signals only, and circuit for optical telecommunications and optical interconnects, for signal readout circuits for a magnetic memory and semiconductor memory, and the like, the input signal levels of which are varied and unclear, for all these circuits, it is important that an input signal level of the preamplifier is detected automatically to determine the optimum operation point and minimize a distortion of waveform of a reproduced pulse.
In order to minimize the distortion, an automatic discrimination type waveform reproduction circuit has been employed which detects and normalizes a peak level of an input pulse signal to always discriminate the pulse signal by half the amplitude of the pulse signal irrespective of variations in the level of the input pulse signal.
Peak detectors are also used for signal surveillance. For instance, input loss of signal (ILOS) detection is crucial for a wide range of devices. Here a peak detector is used to indicate whether a signal is absent by detecting no peaks.
It is a sample-and-hold peak detector circuit that is important in common to the foregoing examples. In particular, it is desirable for a circuit for processing a signal with an arbitrary pattern, such as the optical interconnection, to respond to a burst waveform and it is important to respond at high speed of not less than nanoseconds in order to correctly detect and hold a peak value of the first-input pulse. Recently there have been great demands that the sample-and-hold peak detector circuit should be relatively small in size or compact so as to be incorporated into an IC without any external capacitor. Also there have been demands for low power consumption in order to incorporate the sample-and-hold peak detector circuit into a multi-channel array, as well as a demand for a compensation of the technology dependent charging and discharging current. A further demand is the technology independence as well as the temperature and power supply independence of the sample-and-hold characteristics. In U.S. Pat. No. 5,986,481 Kaminshi describes the fundamental arrangements of known prior art sample-and-hold peak detector circuits, illustrated in FIG.
1
and FIG.
2
. The operation principle of each circuit is as follows. In the circuit of
FIG. 1
, a pulse input to an input terminal of a differential amplifier constituted of transistors T
1
and T
2
, is compared with an output voltage of the sample-and-hold peak detector circuit and, if the voltage of the input pulse is higher than the output voltage with respect to Vee, an error is amplified and the base voltage of a switching transistor T
3
is increased. Transistor T
3
is turned on to start discharging a voltage holding capacitor C
1
. When the output voltage of the emitter follower circuit of a transistor T
4
reaches the voltage of the input peak, the base voltage of the transistor T
3
is lowered to cut off the current flowing into the transistor T
3
. If the top voltage of the input pulse is maintained until the current is cut off the voltage with which the voltage holding capacitor C
1
is discharged, becomes equal to the peak voltage of the input pulse.
Since the leak peak current of the transistor T
4
is low, the time constant of charging of the capacitor is large and its peak voltage is maintained.
The operation of the switching transistor T
3
will be described in more detail. The transistor T
3
is a bipolar transistor and thus has a characteristic of causing a current to flow exponentially with respect to a base-to-emitter voltage. When the amplitude of base-to-emitter voltage is small, the dynamic impedance is high, the injected current is small, and the peak transit time is long. On the other hand, when the amplitude exceeds a certain value, the impedance is drastically lowered and the charging time is too short, with the result that a feedback is delayed and so is the cutoff of the switching transistor, thus causing an overshoot of the output voltage.
Consequently, an input voltage range for normally operating the circuit is restricted, and it is difficult to widen an input dynamic range. If the input voltage is too high, a collector current may flow through the transistors beyond a tolerable range, and the cutoff frequency may decrease, thereby causing a delay in response.
A circuit capable of excluding the above drawbacks to some extent, is shown in FIG.
2
. In the circuit of
FIG. 2
, the voltage holding capacitor C
1
is charged with a current which is almost proportional to the amplitude of an error voltage by a current output amplifier using a PNP transistor in place of a switch of an NPN transistor (shown in
FIG. 1
) with drastically changing impedance. In the circuit of
FIG. 2
, a power supply voltage needs to be higher than that of the circuit of FIG.
1
and the PNP transistor should satisfy a high speed operation.
In general, however, the bandwidth of the PNP transistor is about one-tenth of that of the NPN transistor; thus, the circuit of
FIG. 2
has an essential problem that a high-speed operation cannot be satisfied.
The problem of the circuit shown in
FIG. 1
on principle is an exponentially, nonlinear response to an input voltage of a switching transistor. However, this problem can be resolved if, as in the circuit of
FIG. 2
, the NPN switching transistor is operated so as to exhibit a linear response to the input voltage.
A high gain feedback amplifier may be useful for the sample-and-hold peak detector circuit in order to linearly operate an element originally having a remarkably nonlinear characteristic. In this case, usually, there occurs a problem that a high-speed operation cannot be carried out due to a delay in a high gain feedback as well as a problem that a large-sized circuit increases in chip area and thus in power consumption.
BRIEF DESCRIPTION OF THE INVENTION
The invention is based on the idea of definable matching characteristics, i.e. definable time parameter via discharge current compensation and defined constant current sources.
The circuit according to the invention consists of four coupled parts: a comparator circuit, a sample and hold circuit, a compensation circuit, and an unload circuit.
The circuitry for generating an output signal representative of peak level signals over a wide frequency range according to the invention comprises a comparator circuit at a first control input t

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