Fast response system implementing a sampling clock for extractin

Details Fast response system implementing a sampling clock for extractin Fast response system implementing a sampling clock for extractin

1995-10-13

1998-10-20

Pham, Chi H.

Pulse or digital communications

Synchronizers

Self-synchronizing signal

375371, 327161, H04L 7033

Patent

active

058258345

ABSTRACT:
The present invention relates to a clock recovery system which allows for stable clock information to be extracted from a serial data stream with defined jitter characteristics. The clock recover circuit is comprised of a flip flop which is used for receiving the serial data stream and for outputting stable clock information. A sampling clock circuit is coupled to the flip flop for sending a signal which reflects a center area of each bit period in the serial data stream when a transition occurs in the serial data stream.

REFERENCES:
patent: 4885758 (1989-12-01), Speckenbach
patent: 5313501 (1994-05-01), Thacker

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