Fast response comparator

Details Fast response comparator Fast response comparator

1996-09-20

1999-02-09

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327307, 327362, H03L 500

Patent

active

058699872

ABSTRACT:
A comparator with output that responds quickly to changes in input. The comparator is made up of three stages, an input sampling network, a first amplifier stage, and a second amplifier stage. The input sampling network interfaces the two voltage levels that are to be compared with the first amplifier stage. The first amplifier stage then generates a low level signal that is dependent on the relative levels of the two inputs and passes the low level signal to the second amplifier stage. The second amplifier stage amplifies the output of the first amplifier stage to a usable level. Superior response time is achieved through by dividing the input sampling network into two stages, an input stage and an offset stage, and decoupling the two stages during offset cancellation.

REFERENCES:
patent: 4429282 (1984-01-01), Saari
patent: 4633223 (1986-12-01), Senderowicz
patent: 4808942 (1989-02-01), Milkovic
patent: 5410270 (1995-04-01), Rybicki et al.
patent: 5506526 (1996-04-01), Seesink
patent: 5617054 (1997-04-01), Koifman et al.
G.M. Yin, F. Op't Eynde, and W. Sansen, "A High-Speed CMOS Comparator with 8-b Resolution", IEEE Journal of Solid-State Circuits, vol. 27 No. 2, Feb. 1992.

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